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Tutorial: Thermal Challenges for Heterogeneous Integration Packaging

November 2 @ 8:00 am - 9:00 pm

Heterogeneous Integration poses several significant challenges for thermal management at multiple length scales ranging from heat extraction from hot spots, heat transfer through multiple layers of materials, different target temperatures for specific devices/materials, to heat rejection to a system cooling solution or the ambient. This applies to system-in-packages, including 2D, 2.5D, and 3D subsystems and the special needs of photonic devices. We need to consider the various thermal paths within packages to dissipate the generated heat, how to apply modeling and simulation, and advanced cooling methods including conduction, liquid cooling, heat pipes, and more exotic designs.
It is important to identify and develop a detailed understanding of the capabilities and limitations of key thermal technologies that meet or exceed these demands so that they are available well in advance of need and can be implemented if they meet integration cost envelopes. We will consider three areas for thermal management: Die level; Package integration/System-in-Package (SIP)/module level; and System level. We will focus on emerging challenges and opportunities for thermal modeling of advanced 3D IC systems; challenges and characterization of hotspot modeling; thermal modeling for High Bandwidth Memory (HBM) and integrated voltage regulators; and innovative methods for manufacturing silicon microchannels.
Speaker(s): Mehdi Asheghi, ,
Virtual: https://events.vtools.ieee.org/m/375984


November 2
8:00 am - 9:00 pm


Virtual: https://events.vtools.ieee.org/m/375984