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Got a Lot of Chip Designin’ to Do

May 1 @ 6:30 pm - 8:00 pm

Chiplets are now the standard way to design chips at leading-edge nodes for applications such as AI and high-performance computing. Obvious challenges include the new stage of heterogeneous integration, the new bus that connects the chiplets, and the new advanced packages that hold it all together. No more afterthoughts; packaging, test, integration, and manufacturing must all start right with the design. And design teams and foundry teams must work closely together to achieve the best result. Power, thermal, and other analyses must evaluate both individual chiplets and the system-as-a-whole (including the package). The foundry will play a larger role than ever before because it will generally provide a choice of packages and perform the integration, and it will need fully tested (known good) dies to avoid wasting time and money on chips that fail inspection.
Speaker(s): Jawad Nasrullah,
Room: 225, Bldg: Heafey, Santa Clara University, Santa Clara, California, United States, Virtual: https://events.vtools.ieee.org/m/477704

Details

Date:
May 1
Time:
6:30 pm - 8:00 pm
Website:
https://events.vtools.ieee.org/m/477704

Venue

Room: 225, Bldg: Heafey, Santa Clara University, Santa Clara, California, United States, Virtual: https://events.vtools.ieee.org/m/477704